Regular, area-time efficient carry-lookahead adders

For fast binary addition, a carry-lookahead (CLA) design is the obvious choice (S. Ong and D. E. Atkins, Proc. Sixth Symposium of Computer Arithmetic, Aarhus, Denmark, June 1983; M. A. Bayoumi, G. A. Jullien, and W. C. Miller, INTEGRATION 1 (1983)). However, the direct implementation of a CLA adder in VLSI faces some undesirable limitations. Either the design lacks regularity, thus increasing the design and implementation costs, or the interconnection wires are too long, thus causing area-time inefficiency and limits on the size of addition. R. P. Brent and H. T. Kung (IEEE Trans. Comput. C-31 (Mar. 1982)) solved the regularity problem by reformulating the carry chain computation. They showed that an n-bit addition can be performed in time O (log n), using area O(n log n) with maximum interconnection wire length O(n). In this paper, we give an alternative log n stage design which is nearly optimum with respect to regularity, area-time efficiency, and maximum interconnection wire length.