Reliability-aware co-synthesis for embedded systems

Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin

Research output: Contribution to journalConference articlepeer-review

47 Scopus citations


As technology scales, transient faults due to single event upsets have emerged as a key challenge for reliable embedded system design. This paper proposes a design methodology that incorporates reliability into hardware-software co-design paradigm for embedded systems. We introduce an allocation and scheduling algorithm that efficiently handles conditional execution in multi-rate embedded systems, and selectively duplicates critical tasks to detect soft errors, such that the reliability of the system is increased. The increased reliability is achieved by utilizing the otherwise idle computation resources and incurs no resource or performance penalty. The proposed algorithm is fast and efficient, and is suitable for use in the inner loop of our hardware/software co-synthesis framework, where the scheduling routine has to be invoked many times.

Original languageEnglish (US)
Pages (from-to)41-50
Number of pages10
JournalProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
StatePublished - 2004
EventProceedings - 15th IEEE International Conference on Applications-Specific Systems, Architectures and Processors - Galveston, TX, United States
Duration: Sep 27 2004Sep 29 2004

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications


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