Reliability-aware SOC voltage Islands partition and floorplan

Shengqi Yang; Wayne Wolf; N. Vijaykrishnan; Yuan Xie

doi:10.1109/ISVLSI.2006.79

Reliability-aware SOC voltage Islands partition and floorplan

Shengqi Yang, Wayne Wolf, N. Vijaykrishnan, Yuan Xie

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip design, for the first time, is illustrated. Voltage island partitioning and floorplanning for System-On-a-Chip (SOC) design is used as a case study for this reliability aware methodology. The proposed methodology partitions all SOC components into different voltage islands with power reduction and guaranteed system reliability. Experiments show that for a typical SOC the algorithm execution time is within several minutes while achieving 12% to 23% power reduction. Extended SOC algorithm partitions and floorplanns the voltage islands within 2.5 to 29.7 minutes and achieved 9.74% to 18.50% power reduction.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages	343-348
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2006.79
State	Published - 2006
Event	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany Duration: Mar 2 2006 → Mar 3 2006

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume	2006

Other

Other	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Country/Territory	Germany
City	Klarlsruhe
Period	3/2/06 → 3/3/06

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/ISVLSI.2006.79

Cite this

Yang, S., Wolf, W., Vijaykrishnan, N., & Xie, Y. (2006). Reliability-aware SOC voltage Islands partition and floorplan. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (pp. 343-348). Article 1602462 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006). https://doi.org/10.1109/ISVLSI.2006.79

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title = "Reliability-aware SOC voltage Islands partition and floorplan",

abstract = "Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip design, for the first time, is illustrated. Voltage island partitioning and floorplanning for System-On-a-Chip (SOC) design is used as a case study for this reliability aware methodology. The proposed methodology partitions all SOC components into different voltage islands with power reduction and guaranteed system reliability. Experiments show that for a typical SOC the algorithm execution time is within several minutes while achieving 12% to 23% power reduction. Extended SOC algorithm partitions and floorplanns the voltage islands within 2.5 to 29.7 minutes and achieved 9.74% to 18.50% power reduction.",

author = "Shengqi Yang and Wayne Wolf and N. Vijaykrishnan and Yuan Xie",

year = "2006",

doi = "10.1109/ISVLSI.2006.79",

language = "English (US)",

isbn = "0769525334",

series = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

pages = "343--348",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

note = "IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 ; Conference date: 02-03-2006 Through 03-03-2006",

}

Yang, S, Wolf, W, Vijaykrishnan, N & Xie, Y 2006, Reliability-aware SOC voltage Islands partition and floorplan. in Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006., 1602462, Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, vol. 2006, pp. 343-348, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, Klarlsruhe, Germany, 3/2/06. https://doi.org/10.1109/ISVLSI.2006.79

Reliability-aware SOC voltage Islands partition and floorplan. / Yang, Shengqi; Wolf, Wayne; Vijaykrishnan, N. et al.
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 343-348 1602462 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip design, for the first time, is illustrated. Voltage island partitioning and floorplanning for System-On-a-Chip (SOC) design is used as a case study for this reliability aware methodology. The proposed methodology partitions all SOC components into different voltage islands with power reduction and guaranteed system reliability. Experiments show that for a typical SOC the algorithm execution time is within several minutes while achieving 12% to 23% power reduction. Extended SOC algorithm partitions and floorplanns the voltage islands within 2.5 to 29.7 minutes and achieved 9.74% to 18.50% power reduction.

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Yang S, Wolf W, Vijaykrishnan N, Xie Y. Reliability-aware SOC voltage Islands partition and floorplan. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 343-348. 1602462. (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006). doi: 10.1109/ISVLSI.2006.79

Reliability-aware SOC voltage Islands partition and floorplan

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