Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems

G. Chen; M. Kandemir; S. Tosun; U. Sezer

doi:10.1109/IPDPS.2005.379

Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems

G. Chen, M. Kandemir, S. Tosun, U. Sezer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.

Original language	English (US)
Title of host publication	Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Pages	162a
DOIs	https://doi.org/10.1109/IPDPS.2005.379
State	Published - Dec 1 2005
Event	19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States Duration: Apr 4 2005 → Apr 8 2005

Publication series

Name	Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Volume	2005

Other

Other	19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Country/Territory	United States
City	Denver, CO
Period	4/4/05 → 4/8/05

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/IPDPS.2005.379

Cite this

Chen, G., Kandemir, M., Tosun, S., & Sezer, U. (2005). Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 (pp. 162a). Article 1420025 (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005). https://doi.org/10.1109/IPDPS.2005.379

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title = "Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems",

abstract = "This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.",

author = "G. Chen and M. Kandemir and S. Tosun and U. Sezer",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/IPDPS.2005.379",

language = "English (US)",

isbn = "0769523129",

series = "Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005",

pages = "162a",

booktitle = "Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005",

note = "19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 ; Conference date: 04-04-2005 Through 08-04-2005",

}

Chen, G, Kandemir, M, Tosun, S & Sezer, U 2005, Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems. in Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005., 1420025, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, vol. 2005, pp. 162a, 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, Denver, CO, United States, 4/4/05. https://doi.org/10.1109/IPDPS.2005.379

Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems. / Chen, G.; Kandemir, M.; Tosun, S. et al.
Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. p. 162a 1420025 (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems

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N2 - This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.

AB - This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.

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M3 - Conference contribution

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T3 - Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

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BT - Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

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Chen G, Kandemir M, Tosun S, Sezer U. Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. p. 162a. 1420025. (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005). doi: 10.1109/IPDPS.2005.379

Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems

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