Abstract
System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.
Original language | English (US) |
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Title of host publication | 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 |
DOIs | |
State | Published - 2011 |
Event | 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of Duration: Aug 7 2011 → Aug 10 2011 |
Other
Other | 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 8/7/11 → 8/10/11 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials