Retention Testing Methodology for STTRAM

Anirudh Iyengar, Swaroop Ghosh, Srikant Srinivasan

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


A design-for-test (DFT) solution to reduce the test time by incorporating a weak write test mode to effectively screen the weak bits from other strong bits is proposed for spin-torque transfer RAM (STTRAM). During burn-in, the chip's temperature is increased to 125°C. The retention time is tested under this condition for multiple iterations to account for stochastic retention. The advantage of testing the retention time during burnin is that it allows an accurate control of the temperature and hence an accurate retention time measurement. Test after burn-in scenario only tests good chips for their retention, thus reducing the impact on the time-to-market. The retention time search is determined by performing write and read operation multiple times with different retention intervals to lower the retention time which allows to test under low-power conditions and with lower test times. Due to the highly compressed test time of the proposed approach we are able to accommodate a reasonable number of iterations in the same test time as compared to the traditional approach, to obtain the worst case retention time.

Original languageEnglish (US)
Article number7513435
Pages (from-to)7-15
Number of pages9
JournalIEEE Design and Test
Issue number5
StatePublished - 2016

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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