Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Yih Wang; Umut Arslan; Nabhendra Bisnik; Ruth Brain; Swaroop Ghosh; Fatih Hamzaoglu; Nick Lindert; Mesut Meterelliyoz; Joodong Park; Shigeki Tomishima; Kevin Zhang

doi:10.1109/IEDM.2013.6724595

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Yih Wang
, Umut Arslan
, Nabhendra Bisnik
, Ruth Brain
, Swaroop Ghosh
, Fatih Hamzaoglu
, Nick Lindert
, Mesut Meterelliyoz
, Joodong Park
, Shigeki Tomishima
, Kevin Zhang

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

Original language	English (US)
Title of host publication	2013 IEEE International Electron Devices Meeting, IEDM 2013
Pages	9.5.1-9.5.4
DOIs	https://doi.org/10.1109/IEDM.2013.6724595
State	Published - 2013
Event	2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States Duration: Dec 9 2013 → Dec 11 2013

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2013 IEEE International Electron Devices Meeting, IEDM 2013
Country/Territory	United States
City	Washington, DC
Period	12/9/13 → 12/11/13

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2013.6724595

Cite this

Wang, Y., Arslan, U., Bisnik, N., Brain, R., Ghosh, S., Hamzaoglu, F., Lindert, N., Meterelliyoz, M., Park, J., Tomishima, S., & Zhang, K. (2013). Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 (pp. 9.5.1-9.5.4). Article 6724595 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724595

@inproceedings{57a71fa9e71743ce8e866bc29e130219,

title = "Retention time optimization for eDRAM in 22nm tri-gate CMOS technology",

abstract = "A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.",

author = "Yih Wang and Umut Arslan and Nabhendra Bisnik and Ruth Brain and Swaroop Ghosh and Fatih Hamzaoglu and Nick Lindert and Mesut Meterelliyoz and Joodong Park and Shigeki Tomishima and Kevin Zhang",

year = "2013",

doi = "10.1109/IEDM.2013.6724595",

language = "English (US)",

isbn = "9781479923076",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "9.5.1--9.5.4",

booktitle = "2013 IEEE International Electron Devices Meeting, IEDM 2013",

note = "2013 IEEE International Electron Devices Meeting, IEDM 2013 ; Conference date: 09-12-2013 Through 11-12-2013",

}

Wang, Y, Arslan, U, Bisnik, N, Brain, R, Ghosh, S, Hamzaoglu, F, Lindert, N, Meterelliyoz, M, Park, J, Tomishima, S & Zhang, K 2013, Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. in 2013 IEEE International Electron Devices Meeting, IEDM 2013., 6724595, Technical Digest - International Electron Devices Meeting, IEDM, pp. 9.5.1-9.5.4, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 12/9/13. https://doi.org/10.1109/IEDM.2013.6724595

TY - GEN

T1 - Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

AU - Wang, Yih

AU - Arslan, Umut

AU - Bisnik, Nabhendra

AU - Brain, Ruth

AU - Ghosh, Swaroop

AU - Hamzaoglu, Fatih

AU - Lindert, Nick

AU - Meterelliyoz, Mesut

AU - Park, Joodong

AU - Tomishima, Shigeki

AU - Zhang, Kevin

PY - 2013

Y1 - 2013

N2 - A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

AB - A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

UR - https://www.scopus.com/pages/publications/84894360401

UR - https://www.scopus.com/pages/publications/84894360401#tab=citedBy

U2 - 10.1109/IEDM.2013.6724595

DO - 10.1109/IEDM.2013.6724595

M3 - Conference contribution

AN - SCOPUS:84894360401

SN - 9781479923076

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 9.5.1-9.5.4

BT - 2013 IEEE International Electron Devices Meeting, IEDM 2013

T2 - 2013 IEEE International Electron Devices Meeting, IEDM 2013

Y2 - 9 December 2013 through 11 December 2013

ER -

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Abstract

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