Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects

Tapobrata Bandyopadhyay, Ki Jin Han, Daehyun Chung, Ritwik Chatterjee, Madhavan Swaminathan, Rao Tummala

Research output: Contribution to journalArticlepeer-review

96 Scopus citations


3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.

Original languageEnglish (US)
Article number5765485
Pages (from-to)893-903
Number of pages11
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Issue number6
StatePublished - Jun 2011

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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