Abstract
3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.
Original language | English (US) |
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Article number | 5765485 |
Pages (from-to) | 893-903 |
Number of pages | 11 |
Journal | IEEE Transactions on Components, Packaging and Manufacturing Technology |
Volume | 1 |
Issue number | 6 |
DOIs | |
State | Published - Jun 2011 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering