Robust CMOS logic technique for building high frequency circuits with efficient pipelining

Engineering

• Nanosecond 100%
• Fine Grain 100%
• Adders 100%
• Circuit Design 100%
• Clock Frequency 100%
• Process Variation 100%

Computer Science

• Pipelining 100%
• Carry-Lookahead Adder 50%
• Process Variation 50%
• Pipeline Stage 50%
• Clock Frequency 50%
• Frequency System 50%
• Logic Family 50%

Keyphrases

• High-frequency Circuits 100%
• Low Latency Design 33%
• High Clock Frequency 33%
• Signal Coupling 33%
• Pipeline Technique 33%
• High-frequency Circuit Design 33%