Selective caching: Avoiding performance valleys in massively parallel architectures

Computer Science

• Policy Management 100%
• Parallel Architectures 100%
• Graphics Processing Unit 100%
• Optimal Performance 50%
• Evaluation Result 50%
• Main Memory 50%
• Cache Hierarchy 50%
• Data Access 50%
• Systems Performance 50%
• Memory Hierarchy 50%
• Multicore Processor 50%
• Chip Memory Access 50%

Keyphrases

• GPGPU 100%
• Massively Parallel Architectures 100%
• Cache Replacement 75%
• On-chip Cache 50%
• Caching 50%
• Optimal Performance 25%
• System Performance 25%
• Evaluation Results 25%
• Multiple Levels 25%
• Cache Hierarchy 25%
• Main Memory 25%
• Memory Hierarchy 25%
• Dynamically Reconfigurable 25%
• Multicore Processors 25%
• Off-chip Memory Access 25%
• Storage Characteristics 25%