TY - GEN
T1 - Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
AU - Ghosh, Swaroop
AU - Mukhopadhyay, Saibal
AU - Kim, Keejong
AU - Roy, Kaushik
PY - 2006
Y1 - 2006
N2 - Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a self-calibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control.
AB - Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a self-calibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control.
UR - http://www.scopus.com/inward/record.url?scp=34547226726&partnerID=8YFLogxK
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U2 - 10.1145/1146909.1147155
DO - 10.1145/1146909.1147155
M3 - Conference contribution
AN - SCOPUS:34547226726
SN - 1595933816
SN - 1595933816
SN - 9781595933812
T3 - Proceedings - Design Automation Conference
SP - 971
EP - 976
BT - 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 43rd Annual Design Automation Conference, DAC 2006
Y2 - 24 July 2006 through 28 July 2006
ER -