TY - GEN
T1 - SHINE
T2 - 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
AU - Nagarajan, Karthikeyan
AU - Ensan, Sina Sayyah
AU - Nasim Imtiaz Khan, Mohammad
AU - Ghosh, Swaroop
AU - Chattopadhyay, Anupam
N1 - Funding Information:
This work is supported by SRC (2847.001), NSF (CNS- 1814710, CNS- 1722557, CCF-1718474, DGE- 1723687 and DGE-1821766) and DARPA Young Faculty Award (D15AP00089). The last author gratefully acknowledges the support of NRF TUM CREATE grant. We also thank Debjyoti Bhattacharjee (NTU, Singapore) for valuable discussions and comments.
Funding Information:
Acknowledgment: This work is supported by SRC (2847.001), NSF (CNS-1814710, CNS-1722557, CCF-1718474, DGE-1723687 and DGE-1821766) and DARPA Young Faculty Award (D15AP00089). The last author gratefully acknowledges the support of NRF TUM CREATE grant. We also thank Debjyoti Bhattacharjee (NTU, Singapore) for valuable discussions and comments.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].
AB - In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].
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U2 - 10.1109/ISLPED.2019.8824979
DO - 10.1109/ISLPED.2019.8824979
M3 - Conference contribution
AN - SCOPUS:85072670203
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - International Symposium on Low Power Electronics and Design, ISLPED 2019
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 July 2019 through 31 July 2019
ER -
