SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing

Karthikeyan Nagarajan; Sina Sayyah Ensan; Mohammad Nasim Imtiaz Khan; Swaroop Ghosh; Anupam Chattopadhyay

doi:10.1109/ISLPED.2019.8824979

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing

Karthikeyan Nagarajan
, Sina Sayyah Ensan
, Mohammad Nasim Imtiaz Khan
, Swaroop Ghosh
, Anupam Chattopadhyay

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].

Original language	English (US)
Title of host publication	International Symposium on Low Power Electronics and Design, ISLPED 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728129549
DOIs	https://doi.org/10.1109/ISLPED.2019.8824979
State	Published - Jul 2019
Event	2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 - Lausanne, Switzerland Duration: Jul 29 2019 → Jul 31 2019

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
Volume	2019-July
ISSN (Print)	1533-4678

Conference

Conference	2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
Country/Territory	Switzerland
City	Lausanne
Period	7/29/19 → 7/31/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/ISLPED.2019.8824979

Cite this

Nagarajan, K., Ensan, S. S., Nasim Imtiaz Khan, M., Ghosh, S., & Chattopadhyay, A. (2019). SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing. In International Symposium on Low Power Electronics and Design, ISLPED 2019 Article 8824979 (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2019-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2019.8824979

Nagarajan, Karthikeyan ; Ensan, Sina Sayyah ; Nasim Imtiaz Khan, Mohammad et al. / SHINE : A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing. International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings of the International Symposium on Low Power Electronics and Design).

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title = "SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing",

abstract = "In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5\% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].",

author = "Karthikeyan Nagarajan and Ensan, \{Sina Sayyah\} and \{Nasim Imtiaz Khan\}, Mohammad and Swaroop Ghosh and Anupam Chattopadhyay",

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Nagarajan, K, Ensan, SS, Nasim Imtiaz Khan, M, Ghosh, S & Chattopadhyay, A 2019, SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing. in International Symposium on Low Power Electronics and Design, ISLPED 2019., 8824979, Proceedings of the International Symposium on Low Power Electronics and Design, vol. 2019-July, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, 7/29/19. https://doi.org/10.1109/ISLPED.2019.8824979

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing. / Nagarajan, Karthikeyan; Ensan, Sina Sayyah; Nasim Imtiaz Khan, Mohammad et al.
International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8824979 (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Nagarajan, Karthikeyan

AU - Ensan, Sina Sayyah

AU - Nasim Imtiaz Khan, Mohammad

AU - Ghosh, Swaroop

AU - Chattopadhyay, Anupam

PY - 2019/7

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N2 - In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].

AB - In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].

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M3 - Conference contribution

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ER -

Nagarajan K, Ensan SS, Nasim Imtiaz Khan M, Ghosh S, Chattopadhyay A. SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing. In International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8824979. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1109/ISLPED.2019.8824979

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing

Abstract

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