TY - GEN
T1 - Side-channel attack on STTRAM based cache for cryptographic application
AU - Khan, Mohammad Nasim Imtiaz
AU - Bhasin, Shivam
AU - Yuan, Alex
AU - Chattopadhyay, Anupam
AU - Ghosh, Swaroop
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/11/22
Y1 - 2017/11/22
N2 - In this paper, we propose a Side Channel Attack (SCA) model on Spin-Torque Transfer RAM (STTRAM) where an adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. Simulation results indicate that by monitoring write current, 50% of keys could be extracted using 2000 traces. Further improvement of attacks on write operation is also proposed. The read current is found to be more susceptible to leak the key. It reveals first byte in only 40 traces and leaks the entire key in as low as 400 traces. The results are then compared with Static RAM (SRAM) based cache. The attack model has been experimentally validated on read operation of commercial MRAM chip (STTRAM variant). Experimental results indicate that the attack can reveal correct key in 15 traces compared to 40 in simulation due to less algorithmic noise. To the best of our knowledge, this is the first comprehensive SCA study for STTRAM based cache for cryptographic application.
AB - In this paper, we propose a Side Channel Attack (SCA) model on Spin-Torque Transfer RAM (STTRAM) where an adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. Simulation results indicate that by monitoring write current, 50% of keys could be extracted using 2000 traces. Further improvement of attacks on write operation is also proposed. The read current is found to be more susceptible to leak the key. It reveals first byte in only 40 traces and leaks the entire key in as low as 400 traces. The results are then compared with Static RAM (SRAM) based cache. The attack model has been experimentally validated on read operation of commercial MRAM chip (STTRAM variant). Experimental results indicate that the attack can reveal correct key in 15 traces compared to 40 in simulation due to less algorithmic noise. To the best of our knowledge, this is the first comprehensive SCA study for STTRAM based cache for cryptographic application.
UR - http://www.scopus.com/inward/record.url?scp=85041661024&partnerID=8YFLogxK
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U2 - 10.1109/ICCD.2017.14
DO - 10.1109/ICCD.2017.14
M3 - Conference contribution
AN - SCOPUS:85041661024
T3 - Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
SP - 33
EP - 40
BT - Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th IEEE International Conference on Computer Design, ICCD 2017
Y2 - 5 November 2017 through 8 November 2017
ER -