Silicon surface treatments in advanced MOS gate processing

Selected aspects of Si surface treatments in MOS gate processing were investigated. The focus was on surface conditioning prior to high-k gate dielectric mist deposition in planar MOS gate configuration and gate oxidation of inside walls of the trench etched in Si substrate. In the former case integrated anhydrous HF chemical oxide etching process lowers EOT as compared to conventional dilute HF etch performed ex situ. Additional in situ step, the UV/NO re-growth of 0.5 nm thick slightly nitrided oxide, further limits formation of an interfacial oxide and decreases EOT. In the case of oxide grown on RIE-delineated surfaces in the trench no reliable gate oxide can be formed without slight etching of RIE damaged silicon surface. No significant difference between the use of sacrificial oxidation and UV/Cl₂ slight etching of walls inside the trench was observed. Trench etching process itself appears to play dominant role in determining reliability of gate oxide in this case.