TY - GEN
T1 - Simultaneous partitioning and frequency assignment for on-chip bus architectures
AU - Srinivasan, Suresh
AU - Li, Lin
AU - Vijaykrishnan, N.
PY - 2005
Y1 - 2005
N2 - In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.
AB - In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.
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U2 - 10.1109/DATE.2005.269
DO - 10.1109/DATE.2005.269
M3 - Conference contribution
AN - SCOPUS:33646936613
SN - 0769522882
SN - 9780769522883
T3 - Proceedings -Design, Automation and Test in Europe, DATE '05
SP - 218
EP - 223
BT - Proceedings - Design, Automation and Test in Europe, DATE '05
T2 - Design, Automation and Test in Europe, DATE '05
Y2 - 7 March 2005 through 11 March 2005
ER -