TY - GEN
T1 - Simultaneous switching noise analysis of reference voltage rails for pseudo differential interfaces
AU - Park, Sung Joo
AU - Choi, Jae Young
AU - Swaminathan, Madhavan
PY - 2012
Y1 - 2012
N2 - Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counterargument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.
AB - Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counterargument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.
UR - http://www.scopus.com/inward/record.url?scp=84874504849&partnerID=8YFLogxK
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U2 - 10.1109/EPEPS.2012.6457840
DO - 10.1109/EPEPS.2012.6457840
M3 - Conference contribution
AN - SCOPUS:84874504849
SN - 9781467325394
T3 - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
SP - 47
EP - 50
BT - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
T2 - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Y2 - 21 October 2012 through 24 October 2012
ER -