Soft Error and Energy Consumption Interactions: A Data Cache Perspective

Lin Li, Vijay Degalahal, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

39 Scopus citations


Energy-efficiency and reliability are two major design constraints in uencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability considering the on-chip data caches. First, we investigate the impact of two commonly used architectural-level leakage reduction approaches on the data reliability. Our results indicate that the eakage optimization techniques can have very di erent reliability behavior as compared to an original cache with no eakage optimizations. Next, we investigate on providing data reliability in an energy-efficient fashion in the presence of soft-errors. In contrast to current commercial caches that treat and protect all data using the same error detection/correction mechanism, we present an adaptive error coding scheme that treats dirty and clean data cache blocks differently. Furthermore, we present an early-write-back scheme that enhances the ability to use a less powerfu error protection scheme for a onger time without sacrificing reliability. Experimental results show that proposed schemes, when used in conjunction, can reduce dynamic energy of error protection components in L1 data cache by 11% on average without impacting the performance or reliability.

Original languageEnglish (US)
Article number1349323
Pages (from-to)132-137
Number of pages6
JournalProceedings of the International Symposium on Low Power Electronics and Design
Issue numberJanuary
StatePublished - 2004
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: Aug 9 2004Aug 11 2004

All Science Journal Classification (ASJC) codes

  • General Engineering


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