Spacer thickness optimization for FinFET-based logic and memories: A device- circuit co-design approach

We present device-circuit co-design techniques for FinFETs, based on spacer thickness optimization. We show that short channel effects in deeply scaled technologies can be mitigated by engineering the spacer thickness to introduce a gate underlap. FinFETs with symmetric and asymmetric gate underlap are presented and their device characteristics are analyzed. The implication of introducing underlap in FinFETs on circuit design is also discussed. We show that spacer thickness optimization leads to 86% lower leakage and 14% lower dynamic energy consumption with comparable performance. We also present the benefits of FinFETs with asymmetric gate underlap in mitigating the read-write conflict in 6T SRAMs. This technique enhances the read stability by 10% with only 3% lower write margin compared to standard FinFET SRAM. In addition, 58% reduction in leakage, 3% lower write time and 3% higher hold stability is achieved at the cost of 19% higher access time and 4% larger area.