Spike propagation path planning on IBM TrueNorth neurosynaptic system

K. D. Fischl; K. Fair; W. Y. Tsai; J. Sampson; A. G. Andreou

doi:10.1049/el.2017.1351

Spike propagation path planning on IBM TrueNorth neurosynaptic system

K. D. Fischl, K. Fair, W. Y. Tsai, J. Sampson, A. G. Andreou

Research output: Contribution to journal › Article › peer-review

Abstract

The authors report on the implementation of a path planning algorithm on the TrueNorth neurosynaptic system. Their implementation exploits processing in the temporal domain within the architectural constraints of the TrueNorth chip to deduce the optimal path. The optimal path is computed on the TrueNorth chip for grid maps with dimensions as large as 173 × 168 nodes consuming ∼70 mW at an operating voltage of 0.8 V.

Original language	English (US)
Pages (from-to)	1023-1025
Number of pages	3
Journal	Electronics Letters
Volume	53
Issue number	15
DOIs	https://doi.org/10.1049/el.2017.1351
State	Published - Jul 20 2017

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el.2017.1351

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abstract = "The authors report on the implementation of a path planning algorithm on the TrueNorth neurosynaptic system. Their implementation exploits processing in the temporal domain within the architectural constraints of the TrueNorth chip to deduce the optimal path. The optimal path is computed on the TrueNorth chip for grid maps with dimensions as large as 173 × 168 nodes consuming ∼70 mW at an operating voltage of 0.8 V.",

author = "Fischl, {K. D.} and K. Fair and Tsai, {W. Y.} and J. Sampson and Andreou, {A. G.}",

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Spike propagation path planning on IBM TrueNorth neurosynaptic system

Abstract

All Science Journal Classification (ASJC) codes

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