TY - JOUR
T1 - SPX64
T2 - A Scratchpad Memory for General-purpose Microprocessors
AU - Singh, Abhishek
AU - Dave, Shail
AU - Zardoshti, Pantea
AU - Brotzman, Robert
AU - Zhang, Chao
AU - Guo, Xiaochen
AU - Shrivastava, Aviral
AU - Tan, Gang
AU - Spear, Michael
N1 - Publisher Copyright:
© 2020 ACM.
PY - 2021/1
Y1 - 2021/1
N2 - General-purpose computing systems employ memory hierarchies to provide the appearance of a single large, fast, coherent memory. In special-purpose CPUs, programmers manually manage distinct, non-coherent scratchpad memories. In this article, we combine these mechanisms by adding a virtually addressed, set-associative scratchpad to a general purpose CPU. Our scratchpad exists alongside a traditional cache and is able to avoid many of the programming challenges associated with traditional scratchpads without sacrificing generality (e.g., virtualization). Furthermore, our design delivers increased security and improves performance, especially for workloads with high locality or that interact with nonvolatile memory.
AB - General-purpose computing systems employ memory hierarchies to provide the appearance of a single large, fast, coherent memory. In special-purpose CPUs, programmers manually manage distinct, non-coherent scratchpad memories. In this article, we combine these mechanisms by adding a virtually addressed, set-associative scratchpad to a general purpose CPU. Our scratchpad exists alongside a traditional cache and is able to avoid many of the programming challenges associated with traditional scratchpads without sacrificing generality (e.g., virtualization). Furthermore, our design delivers increased security and improves performance, especially for workloads with high locality or that interact with nonvolatile memory.
UR - http://www.scopus.com/inward/record.url?scp=85099784949&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85099784949&partnerID=8YFLogxK
U2 - 10.1145/3436730
DO - 10.1145/3436730
M3 - Article
AN - SCOPUS:85099784949
SN - 1544-3566
VL - 18
JO - ACM Transactions on Architecture and Code Optimization
JF - ACM Transactions on Architecture and Code Optimization
IS - 1
M1 - 14
ER -