TY - JOUR
T1 - SRAMs and DRAMs with separate read-write ports augmented by phase transition materials
AU - Shen, Zhesheng
AU - Srinivasa, Srivatsa
AU - Aziz, Ahmedullah
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
AU - Gupta, Sumeet Kumar
N1 - Funding Information:
Manuscript received October 13, 2018; revised December 13, 2018; accepted December 15, 2018. Date of publication January 4, 2019; date of current version January 22, 2019. This work was supported in part by the Center for Low Energy Systems Technology sponsored by MARCO and DARPA. The review of this paper was arranged by Editor C. M. Compagnoni. (Corresponding author: Zhesheng Shen.) Z. Shen, A. Aziz, and S. K. Gupta are with Purdue University, West Lafayette, IN 47907 USA (e-mail: [email protected]; aziz5@ purdue.edu; [email protected]).
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2019/2
Y1 - 2019/2
N2 - We propose SRAMs and DRAM with independent read-write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads.
AB - We propose SRAMs and DRAM with independent read-write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads.
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U2 - 10.1109/TED.2018.2888913
DO - 10.1109/TED.2018.2888913
M3 - Article
AN - SCOPUS:85060448970
SN - 0018-9383
VL - 66
SP - 929
EP - 937
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 2
M1 - 8601374
ER -