TY - GEN
T1 - Staggered latch bus
T2 - 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
AU - Eze, Melvin
AU - Ozturk, Ozcan
AU - Narayanan, Vijaykrishnan
PY - 2013
Y1 - 2013
N2 - Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.
AB - Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.
UR - http://www.scopus.com/inward/record.url?scp=84899524180&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84899524180&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2013.6673296
DO - 10.1109/VLSI-SoC.2013.6673296
M3 - Conference contribution
AN - SCOPUS:84899524180
SN - 9781479905249
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 296
EP - 301
BT - 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
PB - IEEE Computer Society
Y2 - 7 October 2013 through 9 October 2013
ER -