Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Melvin Eze; Ozcan Ozturk; Vijaykrishnan Narayanan

doi:10.1109/VLSI-SoC.2013.6673296

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Melvin Eze, Ozcan Ozturk, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.

Original language	English (US)
Title of host publication	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
Publisher	IEEE Computer Society
Pages	296-301
Number of pages	6
ISBN (Print)	9781479905249
DOIs	https://doi.org/10.1109/VLSI-SoC.2013.6673296
State	Published - 2013
Event	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey Duration: Oct 7 2013 → Oct 9 2013

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Other

Other	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
Country/Territory	Turkey
City	Istanbul
Period	10/7/13 → 10/9/13

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2013.6673296

Cite this

Eze, M., Ozturk, O., & Narayanan, V. (2013). Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings (pp. 296-301). Article 6673296 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2013.6673296

Eze, Melvin ; Ozturk, Ozcan ; Narayanan, Vijaykrishnan. / Staggered latch bus : A reliable offset switched architecture for long on-chip interconnect. 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society, 2013. pp. 296-301 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

@inproceedings{85f290c0fb6a4217a4de8b80a29b606c,

title = "Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect",

abstract = "Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.",

author = "Melvin Eze and Ozcan Ozturk and Vijaykrishnan Narayanan",

year = "2013",

doi = "10.1109/VLSI-SoC.2013.6673296",

language = "English (US)",

isbn = "9781479905249",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

publisher = "IEEE Computer Society",

pages = "296--301",

booktitle = "2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings",

address = "United States",

note = "2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 ; Conference date: 07-10-2013 Through 09-10-2013",

}

Eze, M, Ozturk, O & Narayanan, V 2013, Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings., 6673296, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, pp. 296-301, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, 10/7/13. https://doi.org/10.1109/VLSI-SoC.2013.6673296

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. / Eze, Melvin; Ozturk, Ozcan; Narayanan, Vijaykrishnan.
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society, 2013. p. 296-301 6673296 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Staggered latch bus

T2 - 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013

AU - Eze, Melvin

AU - Ozturk, Ozcan

AU - Narayanan, Vijaykrishnan

PY - 2013

Y1 - 2013

N2 - Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.

AB - Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.

UR - http://www.scopus.com/inward/record.url?scp=84899524180&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84899524180&partnerID=8YFLogxK

U2 - 10.1109/VLSI-SoC.2013.6673296

DO - 10.1109/VLSI-SoC.2013.6673296

M3 - Conference contribution

AN - SCOPUS:84899524180

SN - 9781479905249

T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

SP - 296

EP - 301

BT - 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings

PB - IEEE Computer Society

Y2 - 7 October 2013 through 9 October 2013

ER -

Eze M, Ozturk O, Narayanan V. Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society. 2013. p. 296-301. 6673296. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2013.6673296

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this