Steep switching hybrid phase transition FETs (Hyper-FET) for low power applications: A device-circuit co-design perspective-part i

Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON (I_ON) and OFF currents (I_OFF). Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity (ρ_INS and ρ_MET respectively) of the PTM needs to be higher than the I_ON I_OFF of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with I_OFF = 0.051μ Aμm and I_ON = 191.5μA/μm , ρ_MET < ∼ 2 × 10^-3 Ω.cm and ∼ 7.5Ω.cm < ρ_INS <20,000 Ω.cm is required to achieve proper device functionality with a boost in I_ON/I_OFF. Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different I_OFF targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger I_ON at iso-I_OFF compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.