TY - JOUR
T1 - Steep switching hybrid phase transition FETs (Hyper-FET) for low power applications
T2 - A device-circuit co-design perspective-part i
AU - Aziz, Ahmedullah
AU - Shukla, Nikhil
AU - Datta, Suman
AU - Gupta, Sumeet Kumar
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2017/3
Y1 - 2017/3
N2 - Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON (ION) and OFF currents (IOFF). Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity (ρINS and ρMET respectively) of the PTM needs to be higher than the ION IOFF of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with IOFF = 0.051μ Aμm and ION = 191.5μA/μm , ρMET < ∼ 2 × 10-3 Ω.cm and ∼ 7.5Ω.cm < ρINS <20,000 Ω.cm is required to achieve proper device functionality with a boost in ION/IOFF. Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different IOFF targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger ION at iso-IOFF compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.
AB - Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON (ION) and OFF currents (IOFF). Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity (ρINS and ρMET respectively) of the PTM needs to be higher than the ION IOFF of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with IOFF = 0.051μ Aμm and ION = 191.5μA/μm , ρMET < ∼ 2 × 10-3 Ω.cm and ∼ 7.5Ω.cm < ρINS <20,000 Ω.cm is required to achieve proper device functionality with a boost in ION/IOFF. Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different IOFF targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger ION at iso-IOFF compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.
UR - http://www.scopus.com/inward/record.url?scp=85009833839&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85009833839&partnerID=8YFLogxK
U2 - 10.1109/TED.2016.2642884
DO - 10.1109/TED.2016.2642884
M3 - Article
AN - SCOPUS:85009833839
SN - 0018-9383
VL - 64
SP - 1350
EP - 1357
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 3
M1 - 7815343
ER -