Study of interface trap density of AlO_xN_y/GaN MOS structures

GaN metal-oxide-semiconductor structures were fabricated by atomic layer deposition of aluminum oxynitride thin films on bulk GaN substrates with c-, a-, and m-plane surfaces. Capacitance-voltage measurements ranging from 5 kHz to 1 MHz were conducted at room temperature. The interface trap number density (Nit) and interface trap level density (Dit) of the devices were extracted. A Nit of less than 2 × 10¹¹ cm⁻² and a Dit of less than 2 × 10¹¹ cm⁻² eV⁻¹ were obtained on the a-plane and m-plane samples. Nit and Dit values were larger for c-plane samples, with the largest interface trap density observed on the c-plane sample with the highest dislocation density. The different Nit and Dit values can be attributed to different dislocation densities and dangling bond densities among different samples.