Substrate-Embedded Microfluidic Cooling of Distributed Vertical Power Delivery Architectures for High-Performance Computing Processors

The advancement of high-performance computing (HPC) demands processors with higher transistor densities and current densities up to 2 A/mm² , posing significant thermal management challenges. Traditional lateral power delivery (LPD) architectures are inadequate due to increased power distribution network (PDN) losses and space constraints. Distributed vertical power delivery (DVPD) architectures with integrated voltage regulators (IVRs) offer a promising solution but introduce substantial thermal issues, especially in 3-D stacked configurations where inner tiers have limited heat dissipation pathways. This article presents PyAEDT-automated numerical simulations of three 48-to-1-V DVPD architectures to investigate thermal behaviors in 3-D stacked designs, with and without substrate-embedded microchannels. The architectures differ in power switch configurations: 1) single-layer embedded gallium nitride (GaN) transistors; 2) dual-layer embedded GaN transistors; and 3) a combination of embedded and flip-chipped GaN transistors. Without microchannels, none of the architectures could maintain operational temperatures below the threshold of 85℃ , with maximum temperatures exceeding 145 ℃ . Incorporating parallel microchannels effectively reduces temperatures below the threshold, enabling 80% system-wide efficiency while supporting high current densities. The required pumping power for microchannel cooling was modest at appropriate flow rates, representing less than 0.1% of the processor’s power consumption. Utilizing PyAEDT automation reduced total simulation time by up to 95% in the studied architectures with microchannels.