TY - JOUR
T1 - System-on-a-Package (SOP) substrate and module with digital, RF and optical integration
AU - Sundaram, Venky
AU - Tummala, Rao
AU - White, George
AU - Lim, Kyutae
AU - Wan, Lixi
AU - Guidotti, Daniel
AU - Liu, Fuhan
AU - Bhattacharya, Swapan
AU - Pulugurtha, Raj M.
AU - Abothu, Isaac Robin
AU - Doraiswami, Ravi
AU - Pucha, Raghuram V.
AU - Laskar, Joy
AU - Tentzeris, Manos
AU - Chang, G. K.
AU - Swaminathan, Madhavan
PY - 2004
Y1 - 2004
N2 - The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve highest system performance at the lowest cost. The microminiaturized multifunctional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the Intelligent Network Communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for System-on-a-Package (SOP) implementation.
AB - The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve highest system performance at the lowest cost. The microminiaturized multifunctional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the Intelligent Network Communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for System-on-a-Package (SOP) implementation.
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M3 - Conference article
AN - SCOPUS:10444289728
SN - 0569-5503
VL - 1
SP - 17
EP - 23
JO - Proceedings - Electronic Components and Technology Conference
JF - Proceedings - Electronic Components and Technology Conference
T2 - 2004 Proceedings - 54th Electronic Components and Technology Conference
Y2 - 1 June 2004 through 4 June 2004
ER -