Targeted random test generation for power-aware multicore designs

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

Research output: Contribution to journalArticlepeer-review


Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre- and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97% to 100% improvement over random MP test coverage.

Original languageEnglish (US)
Article number25
JournalACM Transactions on Design Automation of Electronic Systems
Issue number3
StatePublished - Jun 2012

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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