TY - GEN
T1 - Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective
AU - Liu, Huichu
AU - Cotter, Matthew
AU - Datta, Suman
AU - Narayanan, Vijay
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.
AB - Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.
UR - http://www.scopus.com/inward/record.url?scp=84876107002&partnerID=8YFLogxK
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U2 - 10.1109/IEDM.2012.6479103
DO - 10.1109/IEDM.2012.6479103
M3 - Conference contribution
AN - SCOPUS:84876107002
SN - 9781467348706
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 25.5.1-25.5.4
BT - 2012 IEEE International Electron Devices Meeting, IEDM 2012
T2 - 2012 IEEE International Electron Devices Meeting, IEDM 2012
Y2 - 10 December 2012 through 13 December 2012
ER -