TY - GEN
T1 - Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
AU - Jao, Nicholas
AU - Srivinasa, Srivatsa
AU - Ramanathan, Akshay
AU - Kim, Minhwan
AU - Sampson, John
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
VI. ACKNOWLEDGEMENTS This work is supported in part by NSF Expeditions in Computing CCF-1317560 and by SRC JUMP center for Research on Intelligent Storage and Processing-in-memory (CRISP)
Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Recent advances in emerging technologies such as monolithic 3D Integration (M3D-IC) and emerging non-volatile memory (eNVM) have enabled to embed logic operations in memory. This alleviates the "memory wall" challenges stemming from the time and power expended on migrating data in conventional Von Neumann computing paradigms. We propose a M3D SRAM dot-product engine for compute in-SRAM support used in applications such as matrix multiplication and artificial neural networks. In addition, we propose a novel computing in RRAM-based memory architecture to efficiently solve the computation intensity of sparse dot products. Specifically, the index assessment of sparse matrix-vector multiplication used in support vector machines (SVM). At maximum throughput, our proposed RRAM architecture achieves 11.3× speed up when compared against a near-memory accelerator.
AB - Recent advances in emerging technologies such as monolithic 3D Integration (M3D-IC) and emerging non-volatile memory (eNVM) have enabled to embed logic operations in memory. This alleviates the "memory wall" challenges stemming from the time and power expended on migrating data in conventional Von Neumann computing paradigms. We propose a M3D SRAM dot-product engine for compute in-SRAM support used in applications such as matrix multiplication and artificial neural networks. In addition, we propose a novel computing in RRAM-based memory architecture to efficiently solve the computation intensity of sparse dot products. Specifically, the index assessment of sparse matrix-vector multiplication used in support vector machines (SVM). At maximum throughput, our proposed RRAM architecture achieves 11.3× speed up when compared against a near-memory accelerator.
UR - http://www.scopus.com/inward/record.url?scp=85084958347&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85084958347&partnerID=8YFLogxK
U2 - 10.1109/NANOARCH47378.2019.181303
DO - 10.1109/NANOARCH47378.2019.181303
M3 - Conference contribution
AN - SCOPUS:85084958347
T3 - NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
BT - NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019
Y2 - 17 July 2019 through 19 July 2019
ER -