Temperature-aware voltage islands architecting in system-on-chip design

W. L. Hung; G. M. Link; Yuan Xie; Vijaykrishnan Narayanan; N. Dhanwada; J. Conner

doi:10.1109/ICCD.2005.103

Temperature-aware voltage islands architecting in system-on-chip design

W. L. Hung, G. M. Link, Yuan Xie, Vijaykrishnan Narayanan, N. Dhanwada, J. Conner

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

44 Scopus citations

Abstract

As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC performance, power, and reliability. In view of this, we present a hybrid optimization approach which aims at temperature reduction and hot spot elimination. We demonstrate that considerable improvement in the thermal distribution of a design can be achieved through careful voltage island partitioning, voltage level assignment, and voltage island floorplanning. The experimental results on MCNC benchmarks show significant improvement on the thermal profiles. To the best of our knowledge, this is the first work to explore the thermal impacts of voltage islands.

Original language	English (US)
Title of host publication	Proceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2005
Pages	689-694
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2005.103
State	Published - Dec 1 2005
Event	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States Duration: Oct 2 2005 → Oct 5 2005

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume	2005
ISSN (Print)	1063-6404

Other

Other	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Country/Territory	United States
City	San Jose, CA
Period	10/2/05 → 10/5/05

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2005.103

Cite this

Hung, W. L., Link, G. M., Xie, Y., Narayanan, V., Dhanwada, N., & Conner, J. (2005). Temperature-aware voltage islands architecting in system-on-chip design. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 689-694). Article 1524227 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.103

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title = "Temperature-aware voltage islands architecting in system-on-chip design",

abstract = "As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC performance, power, and reliability. In view of this, we present a hybrid optimization approach which aims at temperature reduction and hot spot elimination. We demonstrate that considerable improvement in the thermal distribution of a design can be achieved through careful voltage island partitioning, voltage level assignment, and voltage island floorplanning. The experimental results on MCNC benchmarks show significant improvement on the thermal profiles. To the best of our knowledge, this is the first work to explore the thermal impacts of voltage islands.",

author = "Hung, {W. L.} and Link, {G. M.} and Yuan Xie and Vijaykrishnan Narayanan and N. Dhanwada and J. Conner",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ICCD.2005.103",

language = "English (US)",

isbn = "0769524516",

series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

pages = "689--694",

booktitle = "Proceedings - 2005 IEEE International Conference on Computer Design",

note = "2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 ; Conference date: 02-10-2005 Through 05-10-2005",

}

Hung, WL, Link, GM, Xie, Y, Narayanan, V, Dhanwada, N & Conner, J 2005, Temperature-aware voltage islands architecting in system-on-chip design. in Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005., 1524227, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2005, pp. 689-694, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, United States, 10/2/05. https://doi.org/10.1109/ICCD.2005.103

Temperature-aware voltage islands architecting in system-on-chip design. / Hung, W. L.; Link, G. M.; Xie, Yuan et al.
Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 689-694 1524227 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Hung, W. L.

AU - Link, G. M.

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AU - Dhanwada, N.

AU - Conner, J.

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N2 - As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC performance, power, and reliability. In view of this, we present a hybrid optimization approach which aims at temperature reduction and hot spot elimination. We demonstrate that considerable improvement in the thermal distribution of a design can be achieved through careful voltage island partitioning, voltage level assignment, and voltage island floorplanning. The experimental results on MCNC benchmarks show significant improvement on the thermal profiles. To the best of our knowledge, this is the first work to explore the thermal impacts of voltage islands.

AB - As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC performance, power, and reliability. In view of this, we present a hybrid optimization approach which aims at temperature reduction and hot spot elimination. We demonstrate that considerable improvement in the thermal distribution of a design can be achieved through careful voltage island partitioning, voltage level assignment, and voltage island floorplanning. The experimental results on MCNC benchmarks show significant improvement on the thermal profiles. To the best of our knowledge, this is the first work to explore the thermal impacts of voltage islands.

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Hung WL, Link GM, Xie Y, Narayanan V, Dhanwada N, Conner J. Temperature-aware voltage islands architecting in system-on-chip design. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 689-694. 1524227. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD.2005.103

Temperature-aware voltage islands architecting in system-on-chip design

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