Temperature-sensitive loop parallelization for chip multiprocessors

Sri Hari Krishna Narayanan; Guilin Chen; Mahmut Kandemir; Yuan Xie

doi:10.1109/ICCD.2005.105

Temperature-sensitive loop parallelization for chip multiprocessors

Sri Hari Krishna Narayanan, Guilin Chen, Mahmut Kandemir, Yuan Xie

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°PC (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.

Original language	English (US)
Title of host publication	Proceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2005
Pages	677-682
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2005.105
State	Published - Dec 1 2005
Event	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States Duration: Oct 2 2005 → Oct 5 2005

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume	2005
ISSN (Print)	1063-6404

Other

Other	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Country/Territory	United States
City	San Jose, CA
Period	10/2/05 → 10/5/05

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICCD.2005.105

Cite this

Narayanan, S. H. K., Chen, G., Kandemir, M., & Xie, Y. (2005). Temperature-sensitive loop parallelization for chip multiprocessors. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 677-682). Article 1524225 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.105

Narayanan, Sri Hari Krishna ; Chen, Guilin ; Kandemir, Mahmut et al. / Temperature-sensitive loop parallelization for chip multiprocessors. Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. pp. 677-682 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

@inproceedings{67c51a5d832d4d36874c514bd5b44833,

title = "Temperature-sensitive loop parallelization for chip multiprocessors",

abstract = "In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°PC (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.",

author = "Narayanan, {Sri Hari Krishna} and Guilin Chen and Mahmut Kandemir and Yuan Xie",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ICCD.2005.105",

language = "English (US)",

isbn = "0769524516",

series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

pages = "677--682",

booktitle = "Proceedings - 2005 IEEE International Conference on Computer Design",

note = "2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 ; Conference date: 02-10-2005 Through 05-10-2005",

}

Narayanan, SHK, Chen, G, Kandemir, M & Xie, Y 2005, Temperature-sensitive loop parallelization for chip multiprocessors. in Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005., 1524225, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2005, pp. 677-682, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, United States, 10/2/05. https://doi.org/10.1109/ICCD.2005.105

Temperature-sensitive loop parallelization for chip multiprocessors. / Narayanan, Sri Hari Krishna; Chen, Guilin; Kandemir, Mahmut et al.
Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 677-682 1524225 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Temperature-sensitive loop parallelization for chip multiprocessors

AU - Narayanan, Sri Hari Krishna

AU - Chen, Guilin

AU - Kandemir, Mahmut

AU - Xie, Yuan

PY - 2005/12/1

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N2 - In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°PC (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.

AB - In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°PC (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.

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T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

SP - 677

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BT - Proceedings - 2005 IEEE International Conference on Computer Design

T2 - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005

Y2 - 2 October 2005 through 5 October 2005

ER -

Narayanan SHK, Chen G, Kandemir M, Xie Y. Temperature-sensitive loop parallelization for chip multiprocessors. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 677-682. 1524225. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD.2005.105

Temperature-sensitive loop parallelization for chip multiprocessors

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