TY - GEN
T1 - Temperature-sensitive loop parallelization for chip multiprocessors
AU - Narayanan, Sri Hari Krishna
AU - Chen, Guilin
AU - Kandemir, Mahmut
AU - Xie, Yuan
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°PC (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.
AB - In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°PC (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.
UR - http://www.scopus.com/inward/record.url?scp=33748555169&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748555169&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2005.105
DO - 10.1109/ICCD.2005.105
M3 - Conference contribution
AN - SCOPUS:33748555169
SN - 0769524516
SN - 9780769524511
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 677
EP - 682
BT - Proceedings - 2005 IEEE International Conference on Computer Design
T2 - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Y2 - 2 October 2005 through 5 October 2005
ER -