TY - GEN
T1 - Test challenges and solutions for emerging non-volatile memories
AU - Khan, Mohammad Nasim Imtiaz
AU - Ghosh, Swaroop
N1 - Funding Information:
This work is supported by Semiconductor Research Corporation (#2727.001), National Science Foundation (#CNS-1722557, #CCF-17l8474 and #DGE-1723687) and DARPA Young Faculty Award (#D15AP00089).
Funding Information:
This work is supported by Semiconductor Research Corporation (#2727.001), National Science Foundation (#CNS1722557, #CCF-17l8474 and #DGE-1723687) and DARPA Young Faculty Award (#D15AP00089).
Publisher Copyright:
© 2018 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.
AB - At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.
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U2 - 10.1109/VTS.2018.8368632
DO - 10.1109/VTS.2018.8368632
M3 - Conference contribution
AN - SCOPUS:85048357078
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 1
EP - 6
BT - Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018
PB - IEEE Computer Society
T2 - 36th IEEE VLSI Test Symposium, VTS 2018
Y2 - 22 April 2018 through 25 April 2018
ER -