Test generation for precise interrupts on out-of-order microprocessors

Validation of precise interrupts on a modern pipelined processor is a non-trivial task. The common approach of asserting external interrupts at random test points offers insufficient coverage, and exhaustive simulation under all pipeline conditions is grossly impractical. This paper describes an enhanced technique for effective verification of a pipelined processor in the event of external interrupts. The paper develops a framework to identify critical points in a test program when resource conflicts and inter-instruction dependencies are large. It is argued that if an external interrupt asserted at the identified points in the test program, then the likelihood of exposing design errors increases.