Test generation in circuits constructed by input decomposition

Gueesang Lee; Mary Jane Irwin; Robert Michael Owens

Test generation in circuits constructed by input decomposition

Gueesang Lee, Mary Jane Irwin, Robert Michael Owens

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors
Publisher	Publ by IEEE
Pages	107-111
Number of pages	5
ISBN (Print)	O81862079X
State	Published - Sep 1990
Event	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA Duration: Sep 17 1990 → Sep 19 1990

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

Other	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
City	Cambridge, MA, USA
Period	9/17/90 → 9/19/90

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

@inproceedings{7a82b67bbc6143bebc2bdec27d6dfde2,

title = "Test generation in circuits constructed by input decomposition",

abstract = "The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.",

author = "Gueesang Lee and Irwin, {Mary Jane} and Owens, {Robert Michael}",

year = "1990",

month = sep,

language = "English (US)",

isbn = "O81862079X",

series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

publisher = "Publ by IEEE",

pages = "107--111",

booktitle = "Proceedings - IEEE International Conference on Computer Design",

note = "Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 ; Conference date: 17-09-1990 Through 19-09-1990",

}

Lee, G, Irwin, MJ & Owens, RM 1990, Test generation in circuits constructed by input decomposition. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Publ by IEEE, pp. 107-111, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 9/17/90.

Test generation in circuits constructed by input decomposition. / Lee, Gueesang; Irwin, Mary Jane; Owens, Robert Michael.
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. p. 107-111 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Test generation in circuits constructed by input decomposition

AU - Lee, Gueesang

AU - Irwin, Mary Jane

AU - Owens, Robert Michael

PY - 1990/9

Y1 - 1990/9

N2 - The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

AB - The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

UR - http://www.scopus.com/inward/record.url?scp=0025486956&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025486956&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025486956

SN - O81862079X

T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

SP - 107

EP - 111

BT - Proceedings - IEEE International Conference on Computer Design

PB - Publ by IEEE

T2 - Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90

Y2 - 17 September 1990 through 19 September 1990

ER -

Test generation in circuits constructed by input decomposition

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this