Test of Supply Noise for Emerging Non-Volatile Memory

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


Emerging Non-Volatile Memories (NVMs) suffer from high read/write current which can result in supply noise such as voltage droop and ground bounce. The magnitude of supply noise depends on the old data and the new data that is being written (for a write operation) or the stored data (for a read operation). In prior work, it has been shown that the noise generated by one access can affect another parallel access. Therefore, parallel read/write operation should be tested considering the supply noise. However, testing for read/write failure with supply noise considerations can take significant test time. In this work, we show that test time can be reduced by 410.82X for RRAM-based NVM Last Level Cache (LLC) by using Design for Test (DFT) circuits such as wordline overdrive and ending write operation early. We also show that the proposed test can save 79.875J of energy compared to the baseline test method.

Original languageEnglish (US)
Title of host publicationInternational Test Conference 2018, ITC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538683828
StatePublished - Jul 2 2018
Event49th IEEE International Test Conference, ITC 2018 - Phoenix, United States
Duration: Oct 29 2018Nov 1 2018

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Conference49th IEEE International Test Conference, ITC 2018
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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