The Design and Implementation of the Arithmetic Cube II, a VLSI Signal Processing System

Robert Michael Owens; Thomas P. Kelliher; Mary Jane Irwin; Mohan Vishwanath; Raminder S. Bajwa; Wen Lin Yang

doi:10.1109/92.250197

The Design and Implementation of the Arithmetic Cube II, a VLSI Signal Processing System

Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder S. Bajwa, Wen Lin Yang

Research output: Contribution to journal › Article › peer-review

Abstract

The Arithmetic Cube II is a high performance signal processing system designed and built at Penn State University. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008 point complex-in complex-out DFT in 3.54 ms. This high performance rate is achieved using very modest technology (2 micron CMOS). This paper provides an overview of the small-n algorithms, then describes the architectural design and implementation of the system, the transform development environment, and reports results of operating the system.

Original language	English (US)
Pages (from-to)	491-502
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	1
Issue number	4
DOIs	https://doi.org/10.1109/92.250197
State	Published - Dec 1993

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/92.250197

Cite this

@article{d1101616379e4545ba9fa4b82514f10e,

title = "The Design and Implementation of the Arithmetic Cube II, a VLSI Signal Processing System",

abstract = "The Arithmetic Cube II is a high performance signal processing system designed and built at Penn State University. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008 point complex-in complex-out DFT in 3.54 ms. This high performance rate is achieved using very modest technology (2 micron CMOS). This paper provides an overview of the small-n algorithms, then describes the architectural design and implementation of the system, the transform development environment, and reports results of operating the system.",

author = "Owens, {Robert Michael} and Kelliher, {Thomas P.} and Irwin, {Mary Jane} and Mohan Vishwanath and Bajwa, {Raminder S.} and Yang, {Wen Lin}",

note = "Funding Information: Manuscript received February 26, 1993; revised June 1, 1993. This work was supported under NSF grants CDA-8914587 and MIP-8902636.",

year = "1993",

month = dec,

doi = "10.1109/92.250197",

language = "English (US)",

volume = "1",

pages = "491--502",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - The Design and Implementation of the Arithmetic Cube II, a VLSI Signal Processing System

AU - Owens, Robert Michael

AU - Kelliher, Thomas P.

AU - Irwin, Mary Jane

AU - Vishwanath, Mohan

AU - Bajwa, Raminder S.

AU - Yang, Wen Lin

N1 - Funding Information: Manuscript received February 26, 1993; revised June 1, 1993. This work was supported under NSF grants CDA-8914587 and MIP-8902636.

PY - 1993/12

Y1 - 1993/12

N2 - The Arithmetic Cube II is a high performance signal processing system designed and built at Penn State University. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008 point complex-in complex-out DFT in 3.54 ms. This high performance rate is achieved using very modest technology (2 micron CMOS). This paper provides an overview of the small-n algorithms, then describes the architectural design and implementation of the system, the transform development environment, and reports results of operating the system.

AB - The Arithmetic Cube II is a high performance signal processing system designed and built at Penn State University. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008 point complex-in complex-out DFT in 3.54 ms. This high performance rate is achieved using very modest technology (2 micron CMOS). This paper provides an overview of the small-n algorithms, then describes the architectural design and implementation of the system, the transform development environment, and reports results of operating the system.

UR - http://www.scopus.com/inward/record.url?scp=0027840056&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027840056&partnerID=8YFLogxK

U2 - 10.1109/92.250197

DO - 10.1109/92.250197

M3 - Article

AN - SCOPUS:0027840056

SN - 1063-8210

VL - 1

SP - 491

EP - 502

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

ER -

The Design and Implementation of the Arithmetic Cube II, a VLSI Signal Processing System

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this