The Design of Error Checkers for Self-Checking Residue Number Arithmetic

W. Kenneth Jenkins

    Research output: Contribution to journalArticlepeer-review

    53 Scopus citations


    During the last few years residue number (RNS) arithmetic has gained increasing importance for providing high speed fault tolerant performance in dedicated digital signal processors. One factor that has limited the use of redundant RNS theory in practice is the hardware complexity of the error checker. This paper presents a mathematical analysis of the error correction algorithm which suggests a new design with considerably reduced hardware complexity. A hardward architecture for a high speed pipelined error checker is proposed.

    Original languageEnglish (US)
    Pages (from-to)388-396
    Number of pages9
    JournalIEEE Transactions on Computers
    Issue number4
    StatePublished - Apr 1983

    All Science Journal Classification (ASJC) codes

    • Software
    • Theoretical Computer Science
    • Hardware and Architecture
    • Computational Theory and Mathematics


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