Abstract
The author reviews number-theoretic techniques for achieving hardware modularity in order to facilitate high data rates, testability, reliability, and fault tolerance in VLSI digital signal processing systems. The theory of RNS (residue number system) error detection and correction is reviewed, and the special properties of modular systems are discussed for providing a rich environment for fault tolerant designs. Questions of reliability and fault tolerance on both the integrated circuit level and higher systems levels are discussed. The design of a convolutional back-projection digital processor for synthetic aperture radar (SAR) image processing is used as an example to investigate appropriate interactions between circuit-level error checking and system-level fault tolerance.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 5-8 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| State | Published - 1991 |
| Event | 1991 IEEE International Symposium on Circuits and Systems Part 1 (of 5) - Singapore, Singapore Duration: Jun 11 1991 → Jun 14 1991 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering