The effect of threshold voltages on the soft error rate

V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Scopus citations

Abstract

Due to technology scaling, smaller devices and lower operating voltages, next generation circuits are highly susceptible to soft errors. Another important problem confronting silicon scaling is static power consumption. In this paper, we analyze the effect of increasing threshold voltage (widely used for reducing static power consumption) on the soft error rate (SER). We find that increasing threshold voltage improves SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses. We also show that clever use of high Vt can improve the robustness of 6T-SRAMs.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
PublisherIEEE Computer Society
Pages503-508
Number of pages6
ISBN (Print)0769520936, 9780769520933
DOIs
StatePublished - 2004
EventProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004 - San Jose, CA, United States
Duration: Mar 22 2004Mar 24 2004

Publication series

NameProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Other

OtherProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
Country/TerritoryUnited States
CitySan Jose, CA
Period3/22/043/24/04

All Science Journal Classification (ASJC) codes

  • General Engineering

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