The potential energy efficiency of vector acceleration

Christophe Lemuet, Jack Sampson, Jean Francois Collard, Norm Jouppi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations


Energy efficiency of computation is quickly becoming a key problem from the chip through the data center. This paper presents the first quantitative study of the potential energy efficiency of vector accelerators. We propose and study a vector accelerator architecture suitable for implementation in a 70nm technology. The vector architecture has a high-bandwidth on-chip cache system coupled to 16 independent memory channels. We show that such an accelerator can achieve speedups of 10X or more on loop kernels in comparison to a quad-issue superscalar uniprocessor, while using less energy. We also introduce run-ahead lanes, a complexity and energy efficient means of tolerating variable latency from crossbar contention, cache bank conflicts, cache misses, and the memory system. Run-ahead lanes only synchronize on dependencies or when explicitly directed.

Original languageEnglish (US)
Title of host publicationProceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC'06
StatePublished - 2006

Publication series

NameProceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC'06

All Science Journal Classification (ASJC) codes

  • General Computer Science


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