Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization

Michael Molter, Rahul Kumar, Sonja Koller, Osama Waqar Bhatti, Nikita Ambasana, Elyse Rosenbaum, Madhavan Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


The effect of temperature on the reliability and performance of electrical components and integrated circuits warrants the inclusion of thermal considerations in the early stages of electronic system design. However, the many design parameters involved in the design of the package and the die or macro placement, along with the use of expensive thermal simulations, poses difficulty for conventional optimization algorithms. To overcome that hurdle, this work proposes an efficient Bayesian optimization algorithm which is demonstrated for two early-stage design problems. First, the proposed algorithm is used for the thermal-aware placement of macros with a variable aspect ratio. Second, the proposed Bayesian optimization algorithm is utilized in a two-stage process to optimize the die placement and the package design parameters of a multi-chip module.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 73rd Electronic Components and Technology Conference, ECTC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages8
ISBN (Electronic)9798350334982
StatePublished - 2023
Event73rd IEEE Electronic Components and Technology Conference, ECTC 2023 - Orlando, United States
Duration: May 30 2023Jun 2 2023

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503


Conference73rd IEEE Electronic Components and Technology Conference, ECTC 2023
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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