Thermal gradient aware clock skew scheduling for FPGAs

FPGAs are gradually becoming an essential flexible-digital solution for automotive and military applications, where operating at extreme ambient temperature conditions reaching 125°C are not uncommon. Operating FPGAs under such high-temperature environments require adequate timing margin to compensate potential delay increase, which worsens the performance of FPGAs. To minimize the performance degradation, we propose a thermal gradient aware clock skew scheduling technique which allocates temperature-adaptive timing margins considering worst case thermal gradients and junction temperature ranges of logic-paths in the design, instead of assigning a worst case timing margin to the entire design. The experimental results shows that our technique extends the operating ambient temperature range with an average about 20% performance im-provement¹.