Thermal trends in emerging Technologies

G. M. Link, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Scopus citations


In the future, the peak temperature of a chip will be a primary design constraint. In order to meet this constraint, temperature must be considered in the earliest phases of the design process. Using a newly developed thermal analysis tool, HS3d, this work explores the thermal profile of devices as technology varies. We show that as technology scales, the hotspot locations can shift from the units with the most switching activity to those with the most low-threshold transistors. We further note that process variations in leakage dominated Technologies can result in significant variations in the hotspot locations, indicating that feedback from thermal sensors will be very important. Finally, this work examines the thermal effects of multi-layer device stacking Technologies, and finds that the vertical temperature difference between layers is much less significant than the horizontal differences due to power density, and as such, vertical placement optimizations will have much smaller impact on hotspot development than a uniform power distribution.

Original languageEnglish (US)
Title of host publicationProceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
Number of pages8
StatePublished - Dec 1 2006
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: Mar 27 2006Mar 29 2006

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295


Other7th International Symposium on Quality Electronic Design, ISQED 2006
Country/TerritoryUnited States
CitySan Jose, CA

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality


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