TY - GEN
T1 - Three-dimensional cache design exploration using 3DCacti
AU - Tsai, Yuh Fang
AU - Xie, Yuan
AU - Vijaykrishnan, N.
AU - Irwin, Mary Jane
PY - 2005
Y1 - 2005
N2 - As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to mitigate the interconnect challenges. In this paper, we explore the architectural design of cache memories using 3D circuits. We present a delay and energy model, 3DCacti, to explore different 3D design options of partitioning a cache. The tool allows partitioning of the cache across different device layers at various levels of granularity. The tool has been validated by comparing its results with those obtained from circuit simulation of custom 3D layouts. We also explore the effects of various cache partitioning parameters and 3D technology parameters on delay and energy to demonstrate the utility of the tool.
AB - As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to mitigate the interconnect challenges. In this paper, we explore the architectural design of cache memories using 3D circuits. We present a delay and energy model, 3DCacti, to explore different 3D design options of partitioning a cache. The tool allows partitioning of the cache across different device layers at various levels of granularity. The tool has been validated by comparing its results with those obtained from circuit simulation of custom 3D layouts. We also explore the effects of various cache partitioning parameters and 3D technology parameters on delay and energy to demonstrate the utility of the tool.
UR - http://www.scopus.com/inward/record.url?scp=33746603614&partnerID=8YFLogxK
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U2 - 10.1109/ICCD.2005.108
DO - 10.1109/ICCD.2005.108
M3 - Conference contribution
AN - SCOPUS:33746603614
SN - 0769524516
SN - 9780769524511
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 519
EP - 524
BT - Proceedings - 2005 IEEE International Conference on Computer Design
T2 - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Y2 - 2 October 2005 through 5 October 2005
ER -