Three-dimensional On-chip Interconnect Architectures

Design of Chip Multiprocessors (CMP) / multicores and System-on-Chip (SoC) architectures by exploiting the increasing device density in a single chip is quite complex mainly because it needs a multiparameter (performance, power, temperature, and reliability) design space exploration. The core of this design lies in providing a scalable on-chip communication mechanism that can facilitate the multiobjective design space trade-offs. The Networkon-Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication design issues, and thus, has been a major research thrust spanning across several design coordinates. These include high performance [158, 159, 225, 251], energyefficient [334, 298, 178], fault-tolerant [87, 82, 243], and area-efficient designs [178, 194, 247]. While all these studies, except a few [159, 178, 194, 247], are targeted for 2-D architectures, we believe that the emerging 3-D technology provides ample opportunities to examine the NoC design space.