Threshold-voltage bias-instability in SiC MOSFETs: effects of stress temperature and level on oxide charge buildup and recovery

In this study we performed slow and fast bias temperature instability (BTI) measurements on n-channel silicon carbide (SiC) metal-oxide-SiC field effect transistors. Threshold voltage (V _th) shifts as well as recovery observed during and after stress applied at different temperatures and stress levels were used to understand the dynamics of charge trapping/capture and detrapping/emission at gate oxide defects. It is deduced from the results that no new defects are created by the stress at the levels used in this study and V _th shifts are due to the injected electron capture and trapping at existing oxide border traps. Positive gate-voltage BTI induced V _th shift is observed to follow a power law on stress time with an exponent, n, dependent on stress temperature and level, such that 0.03 ⩽ n ⩽ 0.09. Electron emission and/or defect interactions are found to proceed with a low activation energy of the order of 0.01 eV and are suggested to be responsible for oxide charge reduction and, consequently, V _th recovery.