Timing analysis for thermally robust clock distribution network design for 3D ICs

Sung Joo Park; Nitish Natu; Madhavan Swaminathan; Byunghyun Lee; Sang Min Lee; Woong Hwan Ryu; Kee Sup Kim

doi:10.1109/EPEPS.2013.6703469

Timing analysis for thermally robust clock distribution network design for 3D ICs

Sung Joo Park, Nitish Natu, Madhavan Swaminathan, Byunghyun Lee, Sang Min Lee, Woong Hwan Ryu, Kee Sup Kim

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper we analyze the effect of thermal gradient on the clock distribution networks in the context of 3D ICs. We also propose novel methods for compensating the thermal effects which have been validated through extensive simulations and preliminary hardware measurements.

Original language	English (US)
Title of host publication	2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013
Publisher	IEEE Computer Society
Pages	69-72
Number of pages	4
ISBN (Print)	9781467325363
DOIs	https://doi.org/10.1109/EPEPS.2013.6703469
State	Published - 2013
Event	2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013 - San Jose, CA, United States Duration: Oct 27 2013 → Oct 30 2013

Publication series

Name	2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013

Conference

Conference	2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013
Country/Territory	United States
City	San Jose, CA
Period	10/27/13 → 10/30/13

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/EPEPS.2013.6703469

Cite this

Park, S. J., Natu, N., Swaminathan, M., Lee, B., Lee, S. M., Ryu, W. H., & Kim, K. S. (2013). Timing analysis for thermally robust clock distribution network design for 3D ICs. In 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013 (pp. 69-72). Article 6703469 (2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013). IEEE Computer Society. https://doi.org/10.1109/EPEPS.2013.6703469

Park, Sung Joo ; Natu, Nitish ; Swaminathan, Madhavan et al. / Timing analysis for thermally robust clock distribution network design for 3D ICs. 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013. IEEE Computer Society, 2013. pp. 69-72 (2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013).

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title = "Timing analysis for thermally robust clock distribution network design for 3D ICs",

abstract = "Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper we analyze the effect of thermal gradient on the clock distribution networks in the context of 3D ICs. We also propose novel methods for compensating the thermal effects which have been validated through extensive simulations and preliminary hardware measurements.",

author = "Park, {Sung Joo} and Nitish Natu and Madhavan Swaminathan and Byunghyun Lee and Lee, {Sang Min} and Ryu, {Woong Hwan} and Kim, {Kee Sup}",

year = "2013",

doi = "10.1109/EPEPS.2013.6703469",

language = "English (US)",

isbn = "9781467325363",

series = "2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013",

publisher = "IEEE Computer Society",

pages = "69--72",

booktitle = "2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013",

address = "United States",

note = "2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013 ; Conference date: 27-10-2013 Through 30-10-2013",

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Park, SJ, Natu, N, Swaminathan, M, Lee, B, Lee, SM, Ryu, WH & Kim, KS 2013, Timing analysis for thermally robust clock distribution network design for 3D ICs. in 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013., 6703469, 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013, IEEE Computer Society, pp. 69-72, 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013, San Jose, CA, United States, 10/27/13. https://doi.org/10.1109/EPEPS.2013.6703469

Timing analysis for thermally robust clock distribution network design for 3D ICs. / Park, Sung Joo; Natu, Nitish; Swaminathan, Madhavan et al.
2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013. IEEE Computer Society, 2013. p. 69-72 6703469 (2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper we analyze the effect of thermal gradient on the clock distribution networks in the context of 3D ICs. We also propose novel methods for compensating the thermal effects which have been validated through extensive simulations and preliminary hardware measurements.

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Park SJ, Natu N, Swaminathan M, Lee B, Lee SM, Ryu WH et al. Timing analysis for thermally robust clock distribution network design for 3D ICs. In 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013. IEEE Computer Society. 2013. p. 69-72. 6703469. (2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013). doi: 10.1109/EPEPS.2013.6703469

Timing analysis for thermally robust clock distribution network design for 3D ICs

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