TY - GEN
T1 - To PIM or Not for Emerging General Purpose Processing in DDR Memory Systems
AU - Devic, Alexandar
AU - Rai, Siddhartha Balakrishna
AU - Sivasubramaniam, Anand
AU - Akel, Ameen
AU - Eilert, Sean
AU - Eno, Justin
N1 - Publisher Copyright:
© 2022 Copyright held by the owner/author(s). Publication rights licensed to ACM.
PY - 2022/6/18
Y1 - 2022/6/18
N2 - As Processing-In-Memory (PIM) hardware matures and starts making its way into normal compute platforms, software has an important role to play in determining what to perform where, and when, on such heterogeneous systems. Taking an emerging class of PIM hardware which provisions a general purpose (RISC-V) processor at each memory bank, this paper takes on this challenging problem by developing a software compilation framework. This framework analyzes several application characteristics-parallelizability, vectorizability, data set sizes, and ofoad costs-to determine what, whether, when and how to ofoad computations to the PIM engines. In the process, it also proposes a vector engine extension to the bank-level RISC-V cores. Using several off-the-shelf C/C++ applications, we demonstrate that PIM is not always a panacea, and a framework such as ours is essential in carefully selecting what needs to be performed where, when and how. The choice of hardware platforms-number of memory banks, relative speeds and capabilities of host CPU and PIM cores, can further impact the "to PIM or not"question.
AB - As Processing-In-Memory (PIM) hardware matures and starts making its way into normal compute platforms, software has an important role to play in determining what to perform where, and when, on such heterogeneous systems. Taking an emerging class of PIM hardware which provisions a general purpose (RISC-V) processor at each memory bank, this paper takes on this challenging problem by developing a software compilation framework. This framework analyzes several application characteristics-parallelizability, vectorizability, data set sizes, and ofoad costs-to determine what, whether, when and how to ofoad computations to the PIM engines. In the process, it also proposes a vector engine extension to the bank-level RISC-V cores. Using several off-the-shelf C/C++ applications, we demonstrate that PIM is not always a panacea, and a framework such as ours is essential in carefully selecting what needs to be performed where, when and how. The choice of hardware platforms-number of memory banks, relative speeds and capabilities of host CPU and PIM cores, can further impact the "to PIM or not"question.
UR - http://www.scopus.com/inward/record.url?scp=85132799161&partnerID=8YFLogxK
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U2 - 10.1145/3470496.3527431
DO - 10.1145/3470496.3527431
M3 - Conference contribution
AN - SCOPUS:85132799161
T3 - Proceedings - International Symposium on Computer Architecture
SP - 231
EP - 244
BT - ISCA 2022 - Proceedings of the 49th Annual International Symposium on Computer Architecture
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 49th IEEE/ACM International Symposium on Computer Architecture, ISCA 2022
Y2 - 18 June 2022 through 22 June 2022
ER -