TY - GEN
T1 - Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing
AU - Hung, W.
AU - Xie, Y.
AU - Vijaykrishnan, N.
AU - Kandemir, M.
AU - Irwin, M. J.
AU - Tsai, Y.
PY - 2004/1/1
Y1 - 2004/1/1
N2 - In this paper, we present an algorithm for the minimization of total power consumption via multiple VDD assignment, multiple VTH assignment, device sizing and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded in genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are given for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier and a 32bit carry adders. From the experimental results, we show that the combination of four low power techniques is the effective way to achieve low power budget.
AB - In this paper, we present an algorithm for the minimization of total power consumption via multiple VDD assignment, multiple VTH assignment, device sizing and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded in genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are given for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier and a 32bit carry adders. From the experimental results, we show that the combination of four low power techniques is the effective way to achieve low power budget.
UR - http://www.scopus.com/inward/record.url?scp=49049120587&partnerID=8YFLogxK
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U2 - 10.1109/LPE.2004.240886
DO - 10.1109/LPE.2004.240886
M3 - Conference contribution
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 144
EP - 149
BT - ISLPED 2004 - Proceedings of the 2004 International Symposium on Low Power Electronics and Design
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2004 International Symposium on Low Power Electronics and Design, ISLPED 2004
Y2 - 9 August 2004 through 11 August 2004
ER -